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  hexfet   power mosfet benefits  improved gate, avalanche and dynamic dv/dt ruggedness  fully characterized capacitance and avalanche soa  enhanced body diode dv/dt and di/dt capability  lead-free applications  high efficiency synchronous rectification in smps  uninterruptible power supply  high speed power switching  hard switched and high frequency circuits s d g gds gate drain source dpak IRFR4615PBF ipak irfu4615pbf v dss 150v r ds(on) typ. 34m max. 42m i d 33a d s g notes   through  are on page 11 s d g d absolute maximum ratings symbol parameter units i d @ t c = 25c continuous drain current, v gs @ 10v i d @ t c = 100c continuous drain current, v gs @ 10v i dm pulsed drain current p d @t c = 25c maximum power dissipation w linear derating factor w/c v gs gate-to-source voltage v dv/dt peak diode recovery  v/ns t j operating junction and t stg storage temperature range soldering temperature, for 10 seconds (1.6mm from case) avalanche characteristics e as (thermally limited) single pulse avalanche energy  mj i ar avalanche current a e ar repetitive avalanche energy mj thermal resistance symbol parameter typ. max. units r jc junction-to-case  ??? 1.045 r ja junction-to-ambient (pcb mount)  ??? 50 r ja junction-to-ambient ??? 110 max. 33 24 140 0.96 300 c/w c a 109 see fig. 14, 15, 22a, 22b, 144 38 -55 to + 175 20 
  
    
  
     form quantity IRFR4615PBF tube/bulk 75 IRFR4615PBF irfr4615trlpbf tape and reel left 3000 irfr4615trlpbf irfu4615pbf i-pak tube/bulk 75 irfu4615pbf d-pak base part number package type standard pack orderable part number
  
  
     
 s d g static @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units v (br)dss drain-to-source breakdown voltage 150 ??? ??? v / . 0.1 / .0 .0 0 0 100 100 . dynamic @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units gfs forward transconductance 35 ??? ??? s q g total gate charge ??? 26 q gs gate-to-source charge ??? 8.6 ??? q gd gate-to-drain ("miller") charge ??? 9.0 ??? q sync total gate charge sync. (q g - q gd ) ??? 17 ??? t d(on) turn-on delay time ??? 15 ??? t r rise time ??? 35 ??? t d(off) turn-off delay time ??? 25 ??? t f fall time ??? 20 ??? c iss input capacitance ??? 1750 ??? c oss output capacitance ??? 155 ??? c rss reverse transfer capacitance ??? 40 ??? c oss eff. (er) effective output capacitance (energy related)  ??? 179 ??? c oss eff. (tr) effective output capacitance (time related)  ??? 382 ??? diode characteristics symbol parameter min. typ. max. units i s continuous source current (body diode) i sm pulsed source current (body diode)  v sd diode forward voltage ??? ??? 1.3 v t rr reverse recovery time ??? 70 ??? t j = 25c v r = 100v, ??? 83 ??? t j = 125c i f = 21a q rr reverse recovery charge ??? 177 ??? t j = 25c di/dt = 100a/ s  ??? 247 ??? t j = 125c i rrm reverse recovery current ??? 4.9 ??? a t j = 25c t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by ls+ld) ns nc 33 140 a na nc ns pf a ??? ??? ??? ??? i d = 21a r g = 7.3 10  v dd = 98v i d = 21a, v ds =0v, v gs = 10v t j = 25c, i s = 21a, v gs = 0v  integral reverse p-n junction diode. conditions v gs = 0v, i d = 250 a reference to 25c, i d = 5ma  v gs = 10v, i d = 21a  v ds = v gs , i d = 100 a v ds = 150v, v gs = 0v v ds = 150v, v gs = 0v, t j = 125c mosfet symbol showing the v ds = 75v conditions v gs = 10v  v gs = 0v v ds = 50v ? = 1.0mhz (see fig.5) v gs = 0v, v ds = 0v to 120v (see fig.11) v gs = 0v, v ds = 0v to 120v  conditions v ds = 50v, i d = 21a i d = 21a v gs = 20v v gs = -20v
   
  
     
 fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.01 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 12v 10v 8.0v 7.0v 6.0v 5.5v bottom 5.0v 60 s pulse width tj = 25c 5.0v 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 12v 10v 8.0v 7.0v 6.0v 5.5v bottom 5.0v 60 s pulse width tj = 175c 5.0v 2 4 6 8 10 12 14 16 v gs , gate-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) t j = 25c t j = 175c v ds = 50v 60 s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 2.5 3.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 21a v gs = 10v 1 10 100 1000 v ds , drain-to-source voltage (v) 10 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0 5 10 15 20 25 30 35 q g , total gate charge (nc) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 120v v ds = 75v vds= 30v i d = 21a
   
  
     
 fig 8. maximum safe operating area fig 10. drain-to-source breakdown voltage fig 7. typical source-drain diode forward voltage fig 11. typical c oss stored energy fig 9. maximum drain current vs. case temperature fig 12. maximum avalanche energy vs. draincurrent 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v sd , source-to-drain voltage (v) 1.0 10 100 1000 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 1 10 100 1000 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) operation in this area limited by r ds (on) tc = 25c tj = 175c single pulse 100 sec 1msec 10msec dc -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , temperature ( c ) 140 145 150 155 160 165 170 175 180 185 190 v ( b r ) d s s , d r a i n - t o - s o u r c e b r e a k d o w n v o l t a g e ( v ) id = 5ma 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 50 100 150 200 250 300 350 400 450 500 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 2.8a 5.3a bottom 21a -20 0 20 40 60 80 100 120 140 160 v ds, drain-to-source voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 e n e r g y ( j ) 25 50 75 100 125 150 175 t c , case temperature (c) 0 5 10 15 20 25 30 35 40 i d , d r a i n c u r r e n t ( a )
   
  
     
 fig 13. maximum effective transient thermal impedance, junction-to-case fig 14. typical avalanche current vs.pulsewidth fig 15. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 14, 15: (for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far in excess of t jmax . this is validated for every part type. 2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 16a, 16b. 4. p d (ave) = average power dissipation per single avalanche pulse. 5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 14, 15). t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figures 13) p d (ave) = 1/2 ( 1.3bvi av ) =   t/ z thjc i av = 2  t/ [1.3bvz th ] e as (ar) = p d (ave) t av 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) c / w 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 0.1 1 10 100 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? j = 25c and tstart = 150c. 0.01 allowed avalanche current vs avalanche pulsewidth, tav, assuming tj = 150c and tstart =25c (single pulse) 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 20 40 60 80 100 120 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1.0% duty cycle i d = 21a j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 ci i / ri ci= i / ri c 4 4 r 4 r 4 ri (c/w) i (sec) 0.02324 0.000008 0.26212 0.000106 0.50102 0.001115 0.25880 0.005407
   
  
     
   
 !"#  $# fig 16. threshold voltage vs. temperature   %
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# &'"#  $# -75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v g s ( t h ) , g a t e t h r e s h o l d v o l t a g e ( v ) i d = 100 a i d = 250ua id = 1.0ma id = 1.0a 0 200 400 600 800 1000 di f /dt (a/ s) 100 200 300 400 500 600 700 800 q r r ( a ) i f = 14a v r = 100v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/ s) 100 200 300 400 500 600 700 800 900 1000 q r r ( a ) i f = 21a v r = 100v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/ s) 0 5 10 15 20 25 30 35 i r r m ( a ) i f = 21a v r = 100v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/ s) 0 5 10 15 20 25 30 i r r m ( a ) i f = 14a v r = 100v t j = 25c t j = 125c
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 fig 23a. switching time test circuit fig 23b. switching time waveforms fig 22b. unclamped inductive waveforms fig 22a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 24a. gate charge test circuit fig 24b. gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr fig 21. )*+
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  p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period ,    
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  international as s embled on ww 16, 2001 in the assembly line "a" or note: "p" in as sembly line pos ition example: lot code 1234 this is an irf r120 wi t h as s e mb l y i ndi cates "l ead-f ree" product (optional) p = d e s i gnat e s l e ad- f r e e a = as s e mb l y s i t e code part number we e k 16 dat e code year 1 = 2001 rect if ier international logo lot code as s e mb l y 34 12 irf r120 116a line a 34 rect if ier logo irf r120 12 assembly lot code year 1 = 2001 dat e code part number we e k 16 "p" in ass embly line position indicates "l ead-f r ee" qual i fi cati on to the cons umer - l evel p = d e s i gnat e s l e ad- f r e e product qualif ied t o the consumer level (optional) note: for the most current drawing please refer to ir website at http://www.irf.com/package/
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   78 line a logo international rectifier or product (opt ional) p = de s i gnat e s l e ad- f r e e a = as s e mb l y s i t e code irf u120 part number we e k 19 dat e code year 1 = 2001 rectifier international logo as s e mb l y lot code irfu120 56 dat e code part number lot code as s e mb l y 56 78 ye ar 1 = 2001 we e k 19 119a indicates lead-free" as s e mbl ed on ww 19, 2001 in the assembly line "a" note: "p" in as s embly line pos ition example: wi t h as s e mb l y this is an irfu120 lot code 5678 note: for the most current drawing please refer to ir website at http://www.irf.com/package/
   
  
     
 
     

 

 
  tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl notes : 1. controlling dimension : millimeter. 2. all dimensions are shown in millimeters ( inches ). 3. outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch note: for the most current drawing please refer to ir website at http://www.irf.com/package/
   
  
     
 ? qualification standards can be found at international rectifier?s web site http://www.irf.com/product-info/reliability ?? applicable version of jedec standard at the time of product release. 
  repetitive rating; pulse width limited by max. junction temperature.   limited by t jmax , starting t j = 25c, l = 0.51mh r g = 25 , i as = 21a, v gs =10v. part not recommended for use above this value .  i sd 21a, di/dt 549a/ s, v dd v (br)dss , t j 175c.   pulse width 400 s; duty cycle 2%.   c oss eff. (tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss .  c oss eff. (er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 to 80% v dss . when mounted on 1" square pcb (fr-4 or g-10 material). for recom mended footprint and soldering techniques refer to application note #an-994       *    !" msl 1 (per jedec j-std-020d ?? ) i-pak not appli cable rohs compliant yes moisture sensitivity level d-pak qualification information ? qualification level industrial (per jedec jesd47f ?? guidelines) ir world headquarters: 101 n. sepulveda blvd., el segundo, california 90245, usa to contact international rectifier, please visit http://www.irf.com/whoto-call/ date comments ? updated datasheet to new ir corporate formatting template ? updated orderable part number from "irfr4615trpbf" to "irfr4615trlpbf", on page 1 revision history 5/16/2013


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